4-Bit Asynchronous UP Counter

Hello friends, welcome to ELECTRONICS ENCYCLOPEDIA. In this article we will study about the 4-bit Asynchronous Counter.
As we know that in Asynchronous Counter, all the flip flops are not clocked simultaneously, output of the previous flip-flop becomes the Clock of the next flip flop. And UP counter means that the counter will count from zero to a predetermined value, as this is the 4-bit counter therefore the counter will count upto decimal 15.
"Number of flip-flops used in the counter is equal to the number of bits to be counted."
So we will use 4 flip-flops.

LOGIC DIAGRAM OF 4-BIT ASYNCHRONOUS UP COUNTER

As shown in the figure, there are 4 J-K negative edge triggered flip flop (A,B,C,D) which are not clocked simultaneously. Output of the A flip-flop i.e, QA drives the clock of the B flip flop and so on.

Note: We can also use T-flip flop instead of J-K flip flop.

4-BIT ASYNCHRONOUS COUNTER

WORKING -  Consider that all the flip-flops are initially in logically 0 state (i.e, QA = QB =QC =QD =0). Since the flip flops are negative edge triggered, so transition from 1 to 0 in the clock pulse will cause the output of A flip-flop, QA to change from 0 to 1. Flip-flop B will change its state when its clock input i.e, QA  changes from 1 to 0. Similarly flip-flop C will change its state when its clock input i.e, QB  changes from 1 to 0. And flip-flop D will change its state when its clock input i.e, QC  changes from 1 to 0. You can easily understand it by seeing the Waveform of the output of the counter as shown in figure below.

OUTPUT WAVEFORM

So at the 15th clock pulse, all the flip-flops were in the logically 1 state and at the 16th clock pulse all the flip-flops will again to logically 0 state. 

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